Ethernet PHY

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MACOM’s portfolio of 10G/40G/100G Ethernet Physical Layer (PHY) devices offers unparalleled performance while maintaining high density at low cost. Integrated high-speed, high performance mixed signal I/O using advanced CMOS process nodes support a variety of optical and copper connectivity interfaces. This allows the Ethernet PHY product line to span rack and cluster connectivity within the data center and seamlessly extend to connect multiple data centers together over DWDM optical links. Advanced features such as in-service eye monitors, traffic monitoring, optical module identification and link training are just a few of the advantages that end users leverage for faster bring up, higher reliability and smarter networks.

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Part Number Ordering Package Product Image Datasheet Max Data Rate (Gbps) Supply Voltage Embedded CDR Features Number of Channels Embedded SerDes I/O Matrix Product Brief Application Notes User Guides
 
S28010 Inquire 17mm 248-pin HFCBGA
S28010_300dpi.png
Datasheet
27.96 2.5, 1.2, 0.9
Yes
Single-chip integrated bi-directional 100G transceiver for direct-detect applications
CAUI and OTL-4.10 compliant 10-lane host interface operates from 10.3 Gbps to 11.22 Gbps
100GBASE-R4 and OTL-4.4 compliant network interface supports 100GBASE-RF at 25.78 Gbps
100GBASE-R4 and OTL-4.4 compliant network interface supports OTU4 at 27.95 Gbps
3-Tap Transmit FIR (pre and post-cursor emphasis)
Programmable 28 Gbps output voltage to over 800mVpp
Integrated CTLE and limiting amp on 10G and 28G receivers
Reference clock at 1/16th or 1/64th the system interface rate
Recovered receive clock output for SyncE applications
Support for optional external VCXO or frequency synthesizer
Optional independent Rx reference clock input
1
Yes
1x1
S28010_Gearbox_PB2179.pdf
S28110 Inquire 19mm 324-pin HFCBGA
S28110+S28115_300dpi.png
Datasheet
27.96 2.5, 1.2, 0.9
Yes
Single-chip integrated bi-directional 100G transceiver for direct-detect applications
CAUI and CPPI compliant 10-lane host & module interface operates from 9.95 Gbps to 11.22 Gbps
OIF CEI-28G-SR compliant module interface supports 100GBASE-R4 at 25.78 Gbps
OIF CEI-28G-SR compliant module interface supports OTU4 at 27.95 Gbps
3-Tap Transmit FIR (pre and post-cursor emphasis) on all 10G and 28G transmitters
Programmable 28 Gbps output voltage to over 800mVpp
Integrated CTLE and limiting amp on 10G and 28G receivers
Receive eye monitors for in service link margin evaluation and receiver optimization
Virtual lane identification and BIP error reporting in both 100GE and 2 x 40GE modes
Any-to-any non blocking cross connect in 10 x 10G mode
Reference clock at 1/16th, 1/32nd or 1/64th the host interface rate
Flexible timing modes including reference timing and recovered clock timing
10
Yes
10x10
Product Brief
S28115 Inquire 19mm 324-pin HFCBGA
S28110+S28115_300dpi.png
Datasheet
25.78 2.5, 1.2, 0.9
Yes
XFI and SFP+ compliant 10-lane host interface
OIF CEI-28G-SR compliant module interface
OIF MLG 1.0 compliant in-band coding
IEEE 802.3 Clause 49 compliant PCS on each 10GE input and output lane
Provisionable lane alignment marker insertion in the MLG mux
Provisionable lane physical lane assignment in the MLG demux
3-Tap Transmit FIR (pre and post-cursor emphasis) on all 10G and 28G transmitters
Programmable 28 Gbps output voltage to over 800mVpp
Integrated CTLE and limiting amp on 10G and 28G receivers
Receive eye monitors for in service link margin evaluation and receiver optimization
Virtual lane identification and BIP error reporting
Reference clock at 1/16th, 1/32nd or 1/64th the host interface rate
Flexible timing modes including reference timing and recovered clock timing
Up to 6 optional clock outputs from any internal clock source
10
Yes
10x10
Product Brief
S28032 Inquire 20mm 361-pin HFCBGA
Datasheet
31.79 2.5, 1.2, 0.95
Yes
100 Gbps PHY for metro & long haul applications generates four synchronous DQPSK pre-coded lanes for DP-QPSK modulation
Operation from 111 Gbps to 127.16 Gbps to support FEC overhead
CAUI and OTL-4.10 compliant 10-lane system interface, or 10-lane or 20-lane SFI-S system interface
DP-DQPSK output drivers from 27.9 Gbps to 31.8 Gbps (per lane) with ± 2UI skew adjustment
Transmit equalization to 3 dB
Programmable output voltage to 800 mVppd
Internal 100 Ω termination on CML inputs
Three cross point switches to change multiplexing order
Support for optional external VCXO for jitter compliance
SPI interface to host controller
Integrated per-lane PRBS generators and checkers
-40°C to 85°C Industrial temperature range
20 x 20 mm, PBGA RoHS compliant package
3.2 W typical power in 10-lane mode
1
Yes
1x1
Product Brief
QT2025 Inquire 13mm 144-pin PBGA
QT2025_300dpi.png
Datasheet
10.52 1.8, 1.2
Yes
1G/10G: 1/10GE LAN/WAN & 1/10GFC
Advanced EDC engine with auto tap weight adjustment & tracking
10G high-speed interface with integrated EDC and transmit wave shaping
XAUI interface with equalization and transmit wave shaping
Integrated loopbacks and test features
Compliant to applicable IEEE & INCITS Specs
1
Yes
1x1
QT2025_PB3031 (1).pdf
QT2225 Inquire 23mm 484-pin BGA
QT2225_300dpi.png
Datasheet
10.52 1.8, 1.2
Yes
Dual port 1G/10G: 1/10GE LAN/WAN & 1/10GFC
Advanced EDC engine with auto tap weight adjustment & advanced tracking
10G high-speed interface with integrated EDC and transmit wave shaping
XAUI interface with equalization and transmit wave shaping
Integrated loopbacks and test features
Compliant to applicable IEEE & INCITS Specs
2
Yes
2x2
QT2225_PB3033 (1).pdf
MATP-10025 Inquire BGA
PRISM_angled.png
Inquire 1 x 53 Gbaud PAM-4 Network Interface
4 x 25 Gbps Host Interface
DSP for 2 km reach over SMF
Integrated FEC
Integrated Linear Modulator Driver
PAM-4 test and diagnostic features
10 x 10 mm BGA
MATP-40050 Inquire BGA
PRISM_angled.png
Inquire 4 x 53 Gbaud PAM-4 Network Interface
8 x 26 Gbps Host Interface
DSP for 2 km reach over SMF
PAM-4 test and diagnostic features
Compact BGA