OTN: Framer/Mapper/FEC

OTN: Framer/Mapper/FEC

MACOM’s OTN Framer/Mapper/FEC family products offer complete portfolio of solutions for 10G, 40G and 100G optical transport networks. They are ideal for high capacity Carrier Ethernet router/switches, Packet Optical Transport systems and DWDM Transport systems. The OTN framer devices integrate high performance Serdes I/O to allow seamless connection to optical and copper modules. The provisional Tri-FEC integration supports G.709 standard RS-FEC as well as high coding gain G.975.1 I.4 EFEC and I.7 UFEC to improve optical link performance, achieve longer reach and offer interoperability flexibility. 

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Part Number Ordering Max Data Rate (Gbps) I/O Matrix Embedded CDR Number of Channels Embedded SerDes Package Supply Voltage Signal Rate OTN Signals I/O Rate Product Image Datasheet Benefits Features Product Brief Application Notes User Guides Errata Datasheet Addendum User Guide BSDL
 
S60101 Inquire 11.19 6x6
Yes
6
Yes
35mm 1155-pin FCBGA
2.5, 1.2, 0.9
10G, 40G
OTU2, OTU2e, OTU5
3.125Gbps, 6.25Gbps, 10Gbps, 11.3Gbps
PQX_300dpi.png
Datasheet
Monolithically integrates 6x industry proven Pemaquid devices for high density 10GE Carrier-Ethernet line cards
Integrates 10GE/40GE MAC/PCS termination, frame generation and RMON functions
Includes Tri-FEC support (Reed-Solomon, G.975.1, I.4 and G.975.1, 1.7)
Integrated DPSK Precoder
Supports latest 40GE transcoding for OTN transport
6x On-chip Fractional-N Clock Synthesizer- only one reference clock is required to generate all line rates
Supports LAN, WIS and all 5 10GE mapping modes outlined in ITU G.Sup43
Supports 10GbE into WIS frame, and then into an OTU-2 (ITU G.Sup43, section 6.1)
Supports 10GbE into OTU-2 via GFP-F mapping with two flow control modes (ITU G.Sup43, section 6.2)
Product Brief
Application Note
Errata
Datasheet Addendum
S50101 Inquire 11.19 5x5
Yes
5
Yes
35mm 1155-pin FCBGA
2.5, 1.2, 0.9
10G, 40G
OTU2, OTU2e, OTU4
3.125Gbps, 6.25Gbps, 10Gbps, 11.3Gbps
PQX_300dpi.png
Datasheet
Monolithically integrates 6x industry proven Yahara devices for high density 10G Multi-Service (SONET/SDH/ 10GE/10G Fiber Channel/8.5G Fiber Channel/OTN) Transponder cards
Includes Tri-FEC support (Reed-Solomon, G.975.1, I.4 and G.975.1, 1.7) for 10G/40G line side while supporting Reed-Solomon for client side
Integrated IO cross connect
Integrated DPSK and DQPSK Precoders
Integrates 10GE/40GE MAC/PCS termination, frame generation and RMON functions
Supports latest 10G FC and 40GE transcoding for OTN transport
On-chip Fractional-N Clock Synthesizer- only one reference clock is required to generate all line rates
Supports LAN, WIS and all 5 10GE mapping modes outlined in ITU G.Sup43
Supports 10GbE into WIS frame, and then into an OTU-2 (ITU G.Sup43, section 6.1)
Supports 10GbE into OTU-2 via GFP-F mapping with two flow control modes (ITU G.Sup43, section 6.2)
Supports Bit Transparency mode - 10GbE mapped directly into OTU-2e/1e at 11.096Gb/s or 11.049Gb/s (ITU G.Sup43, section 7.1 & 7.2)
Product Brief
Application Note
Errata
Datasheet Addendum
S40101 Inquire 11.19 4x4
Yes
4
Yes
35mm 1155-pin FCBGA
2.5, 1.2, 0.9
10G, 40G
OTU2, OTU2e, OTU3
3.125Gbps, 6.25Gbps, 10Gbps, 11.3Gbps
PQX_300dpi.png
Datasheet
Monolithically integrates 4x industry proven Pemaquid devices for high density 10GE Carrier-Ethernet line cards
Software API compatible with industry proven Pemaquid device
Integrates 10GE/40GE MAC/PCS termination, frame generation and RMON functions
Includes Tri-FEC support (Reed-Solomon, G.975.1, I.4 and G.975.1, 1.7) for both 10G and 40G
Integrated DPSK Precoder
4x On-chip Fractional-N Clock Synthesizer- only one reference clock is required to generate all line rates
Supports latest 40GE transcoding for OTN transport
Supports LAN, WIS and OTN with 5 different 10GE mapping modes outlined in ITU G.Sup43
Supports 10GbE into WIS frame, and then into an OTU-2 (ITU G.Sup43, section 6.1)
Supports 10GbE into OTU-2 via GFP-F mapping with two flow control modes (ITU G.Sup43, section 6.2)
Bit Transparency mode - 10GbE mapped directly into OTU-2e/1e at 11.096Gb/s or 11.049Gb/s (ITU G.Sup43, section 7.1 & 7.2)
Product Brief
Application Note
Errata
Datasheet Addendum
S20101 Inquire 11.19 2x2
Yes
4
Yes
35mm 1155-pin FCBGA
2.5, 1.2, 0.9
10G
OTU2, OTU2e
3.125Gbps, 6.25Gbps, 10Gbps, 11.3Gbps
PQX_300dpi.png
Datasheet
Monolithically integrates 2x industry proven Pemaquid devices for high density 10GE Carrier-Ethernet line cards
Integrates 10GE MAC/PCS termination, frame generation and RMON functions
Software API compatible with industry proven Pemaquid
Includes Tri-FEC support (Reed-Solomon, G.975.1, I.4 and G.975.1, 1.7) for both 10G and 40G
On-chip Fractional-N Clock Synthesizer- only one reference clock is required to generate all line rates
Supports LAN, WIS and OTN with 5 differnt 10GE mapping modes outlined in ITU G.Sup43
Full OTN and SONET/SDH (WIS compliant) overhead monitoring with overhead drop/insert support
16-bit, 66 MHz microprocessor IF
S20101_PQ20E_PB2166 (1).pdf
Application Note
Errata
Datasheet Addendum
S10126 Inquire 11.3 1x1
Yes
1
Yes
19mm 324-pin FCBGA
2.5, 1.8, 1.2
10G
OTU2, OTU2e
10Gbps, 11.3Gbps
Yahara_30dpi.png
Datasheet
Supports 10GBase-R/10GBaseW, OC-192/STM64, 8G/10G FC, OTU-2 (Standard and Overclocked) Client Signals Extensive Client Mapping Solutions into WIS and OTU-2 Line signals, including Bit Transparency, GFP-T/F, and WIS Optical Line / Client Interfaces
Two 10G Serial Interfaces supporting specific Line/Client baud rates from 8.5Gb/s to 11.32Gb/s
Glue-less Interface to pluggable XFP/SFP+/ MSA modules Backplane Interface
SFI4.1 (16 x 622Mb/s to 708 Mb/s) Interface shared with Optical Client Interface
XAUI (3.125Gb/s or 3.1875Gb/s)
SFI4.2 (2.19Gb/s to 2.94Gb/s)
SFI-5s (2.125Gb/s to 2.85Gb/s)
Fully Compliant to IEEE802.3- 2005, ITU G.709, and XFP4.0 Standards On-Chip Fractional Clock Management Unit - only one reference clock required to generate all line rates for Metro/Carrier Ethernet Applications
Client Pass through support for LAN PHY and WAN PHY applications
Product Brief
S10123_24_26_yahara_AN3175_03_PCB_Layout_Recommendations.pdf
Errata
Datasheet Addendum
User Guide
S10124 Inquire 11.3 1x2
Yes
1
Yes
25mm 576-pin FCBGA
2.5, 1.8, 1.2
10G
OTU2, OTU2e
706Mbps, 3.125Gbps, 10Gbps, 11.3Gbps
Yahara_30dpi.png
Datasheet
Supports 10GBase-R/10GBaseW, OC-192/STM64, 8G/10G FC, OTU-2 (Standard and Overclocked) Client Signals Extensive Client Mapping Solutions into WIS and OTU-2 Line signals, including Bit Transparency, GFP-T/F, and WIS Optical Line / Client Interfaces
Two 10G Serial Interfaces supporting specific Line/Client baud rates from 8.5Gb/s to 11.32Gb/s
Glue-less Interface to pluggable XFP/SFP+/ MSA modules Backplane Interface
SFI4.1 (16 x 622Mb/s to 708 Mb/s) Interface shared with Optical Client Interface
XAUI (3.125Gb/s or 3.1875Gb/s)
SFI4.2 (2.19Gb/s to 2.94Gb/s)
SFI-5s (2.125Gb/s to 2.85Gb/s)
Fully Compliant to IEEE802.3- 2005, ITU G.709, and XFP4.0 Standards On-Chip Fractional Clock Management Unit - only one reference clock required to generate all line rates for Metro/Carrier Ethernet Applications
Client Pass through support for LAN PHY and WAN PHY applications
Product Brief
S10123_24_26_yahara_AN3175_03_PCB_Layout_Recommendations.pdf
Errata
Datasheet Addendum
User Guide
S10123 Inquire 11.3 1x1
Yes
1
Yes
19mm 324-pin FCBGA
2.5, 1.8, 1.2
10G
OTU2, OTU2e
3.125Gbps, 10Gbps, 11.3Gbps
Yahara_30dpi.png
Datasheet
Supports 10GBase-R/10GBaseW, OC-192/STM64, 8G/10G FC, OTU-2 (Standard and Overclocked) Client Signals Extensive Client Mapping Solutions into WIS and OTU-2 Line signals, including Bit Transparency, GFP-T/F, and WIS Optical Line / Client Interfaces
Two 10G Serial Interfaces supporting specific Line/Client baud rates from 8.5Gb/s to 11.32Gb/s
Glue-less Interface to pluggable XFP/SFP+/ MSA modules Backplane Interface
SFI4.1 (16 x 622Mb/s to 708 Mb/s) Interface shared with Optical Client Interface
XAUI (3.125Gb/s or 3.1875Gb/s)
SFI4.2 (2.19Gb/s to 2.94Gb/s)
SFI-5s (2.125Gb/s to 2.85Gb/s)
Fully Compliant to IEEE802.3- 2005, ITU G.709, and XFP4.0 Standards On-Chip Fractional Clock Management Unit - only one reference clock required to generate all line rates for Metro/Carrier Ethernet Applications
Client Pass through support for LAN PHY and WAN PHY applications
Product Brief
S10123_24_26_yahara_AN3175_03_PCB_Layout_Recommendations.pdf
Errata
Datasheet Addendum
User Guide
S12411 Inquire 28 12x12
Yes
12
Yes
29mm 783-pin FCBGA
1.8, 1.5, 1.2, 0.9
10G, 40G, 100G
OTU2, OTU2e, OTU3, OTU5
10Gbps, 11.3Gbps, 25Gbps, 28Gbps
X240_300dpi.png
Datasheet
X120/X240 delivers unprecedented port density and feature integration, providing a power-, cost-, and footprint-optimized solution to Carrier Ethernet router/switch, packet optical transport, and DWDM system
High speed, high performance IOs supports seamless connections to a variety of 10G, 40G and 100G optical and copper connectivity interfaces, including the new 100G CFP2, CFP4 and QSFP28 modules
Integration of 100G Gearbox function significantly optimizes total solution cost and power
The DWDM OTN, EDC and high-gain FEC enables longer transmission distance
Delivers industry leading high-gain, low latency enhanced FEC for 100G networks
Features time stamping features for 1588v2 and Y.1731 OAM
IEEE802.3AE compliant MACSec option provides a low cost, wire-rate security solution to data center and cloud based networks
Fractional synthesizer and jitter attenuation PLLs are integrated to optimize total solution cost and enable high port density design
IEEE802.3 compliant 10GE/40GE/100GE MAC and PCS, and mapping of Ethernet signal into OTU2/2e/1e, OTU3 and OTU4 digital wrapper signal
IEEE standard compliant 1588 PTP timestamp and SyncE support to enable precise and accurate timing synchronization for Ethernet network
IEEE 802.1AE compliant MACSec for 10GE, 40GE and 100GE to provide secured services
Direct connection to XFP, SR/LR/ER/ZR and DWDM SFP+, QSFP+, CFP, CFP2, CFP4, QSFP28, 100G MSA optics and SFP+, QSFP+ Direct Attach Copper modules
Interlaken system packet interface
I/O cross-connect on high speed I/O supports protection switching and eases PCB design
Tri-FEC (G.709 RS-FEC, G.975.1 I.4 EFEC and I.7 UFEC) for 10G and 40G
Integrated fractional synthesizer and jitter attenuation PLL enables single reference clock for all protocols and rates
Extensive diagnostic features including in-system eye monitor for high speed I/Os, loopbacks, PRBS and Packet generators/checkers
Product Brief
Product Overview
Application Note
Application Note
S12312 Inquire 11.2 24x24
Yes
24
Yes
42.5mm 1680-pin FCBGA
1.8, 1.5, 1.2, 0.9
10G, 40G, 100G
OTU2, OTU2e, OTU3, OTU4
10 Gbps, 11.3 Gbps
X240_300dpi.png
Datasheet
X120/X240 delivers unprecedented port density and feature integration, providing a power-, cost-, and footprint-optimized solution to Carrier Ethernet router/switch, packet optical transport, and DWDM systems
Integration of 100G Gearbox function significantly optimizes total solution cost and power
High speed, high performance IOs supports seamless connections to a variety of 10G, 40G and 100G optical and copper connectivity interfaces, including the new 100G CFP2, CFP4 and QSFP28 modules
The DWDM OTN, EDC and high-gain FEC enables longer transmission distance
Delivers industry leading high-gain, low latency enhanced FEC for 100G networks
Features time stamping features for 1588v2 and Y.1731 OAM
IEEE802.3AE compliant MACSec option provides a low cost, wire-rate security solution to data center and cloud based networks
Fractional synthesizer and jitter attenuation PLLs are integrated to optimize total solution cost and enable high port density design
IEEE802.3 compliant 10GE/40GE/100GE MAC and PCS, and mapping of Ethernet signal into OTU2/2e/1e, OTU3 and OTU4 digital wrapper signal
IEEE standard compliant 1588 PTP timestamp and SyncE support to enable precise and accurate timing synchronization for Ethernet network
IEEE 802.1AE compliant MACSec for 10GE, 40GE and 100GE to provide secured services
Direct connection to XFP, SR/LR/ER/ZR and DWDM SFP+, QSFP+, CFP, CFP2, CFP4, QSFP28, 100G MSA optics and SFP+, QSFP+ Direct Attach Copper modules
Interlaken system packet interface
I/O cross-connect on high speed I/O supports protection switching and eases PCB design
Tri-FEC (G.709 RS-FEC, G.975.1 I.4 EFEC and I.7 UFEC) for 10G and 40G
Integrated fractional synthesizer and jitter attenuation PLL enables single reference clock for all protocols and rates
Extensive diagnostic features including in-system eye monitor for high speed I/Os, loopbacks, PRBS and Packet generators/checkers
Product Overview
Application Note
Application Note
S12412 Inquire 27.96 24x24
Yes
24
Yes
42.5mm 1680-pin FCBGA
1.8, 1.5, 1.2, 0.9
10G, 40G, 100G
OTU2, OTU2e, OTU3, OTU6
10 Gbps, 11.3 Gbps, 25 Gbps, 28 Gbps
X240_300dpi.png
Datasheet
X120/X240 delivers unprecedented port density and feature integration, providing a power-, cost-, and footprint-optimized solution to Carrier Ethernet router/switch, packet optical transport, and DWDM systems
Integration of 100G Gearbox function significantly optimizes total solution cost and power
High speed, high performance IOs supports seamless connections to a variety of 10G, 40G and 100G optical and copper connectivity interfaces, including the new 100G CFP2, CFP4 and QSFP28 modules
The DWDM OTN, EDC and high-gain FEC enables longer transmission distance
Delivers industry leading high-gain, low latency enhanced FEC for 100G networks
Features time stamping features for 1588v2 and Y.1731 OAM
IEEE802.3AE compliant MACSec option provides a low cost, wire-rate security solution to data center and cloud based networks
Fractional synthesizer and jitter attenuation PLLs are integrated to optimize total solution cost and enable high port density design
IEEE802.3 compliant 10GE/40GE/100GE MAC and PCS, and mapping of Ethernet signal into OTU2/2e/1e, OTU3 and OTU4 digital wrapper signal
IEEE standard compliant 1588 PTP timestamp and SyncE support to enable precise and accurate timing synchronization for Ethernet network
IEEE 802.1AE compliant MACSec for 10GE, 40GE and 100GE to provide secured services
Direct connection to XFP, SR/LR/ER/ZR and DWDM SFP+, QSFP+, CFP, CFP2, CFP4, QSFP28, 100G MSA optics and SFP+, QSFP+ Direct Attach Copper modules
Interlaken system packet interface
I/O cross-connect on high speed I/O supports protection switching and eases PCB design
Tri-FEC (G.709 RS-FEC, G.975.1 I.4 EFEC and I.7 UFEC) for 10G and 40G
Integrated fractional synthesizer and jitter attenuation PLL enables single reference clock for all protocols and rates
Extensive diagnostic features including in-system eye monitor for high speed I/Os, loopbacks, PRBS and Packet generators/checkers
Product Brief
Product Overview
Application Note
Application N ote
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