Ethernet PHY

MACOM’s portfolio of 10G/40G/100G Ethernet Physical Layer (PHY) devices offers unparalleled performance while maintaining high density at low cost. Integrated high-speed, high performance mixed signal I/O using advanced CMOS process nodes support a variety of optical and copper connectivity interfaces. This allows the Ethernet PHY product line to span rack and cluster connectivity within the data center and seamlessly extend to connect multiple data centers together over DWDM optical links. Advanced features such as in-service eye monitors, traffic monitoring, optical module identification and link training are just a few of the advantages that end users leverage for faster bring up, higher reliability and smarter networks.

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releaseDate	Part Number	Ordering	Package	Datasheet	Max Data Rate (Gbps)	Supply Voltage	Number of Channels	Embedded CDR	I/O Matrix	Embedded SerDes	Product Image	Features	Product Brief	Application Notes	User Guides	Quick Setup Guide	Errata	Evaluation Board User Guide	Software	Brightcove Video

2017/06/19	S28010	Inquire	17mm 248-pin HFCBGA	Datasheet	27.96	2.5, 1.2, 0.9	1	Yes	1x1	Yes	S28010_300dpi.png	Single-chip integrated bi-directional 100G transceiver for direct-detect applications CAUI and OTL-4.10 compliant 10-lane host interface operates from 10.3 Gbps to 11.22 Gbps 100GBASE-R4 and OTL-4.4 compliant network interface supports 100GBASE-RF at 25.78 Gbps 100GBASE-R4 and OTL-4.4 compliant network interface supports OTU4 at 27.95 Gbps 3-Tap Transmit FIR (pre and post-cursor emphasis) Programmable 28 Gbps output voltage to over 800mVpp Integrated CTLE and limiting amp on 10G and 28G receivers Reference clock at 1/16th or 1/64th the system interface rate Recovered receive clock output for SyncE applications Support for optional external VCXO or frequency synthesizer Optional independent Rx reference clock input	S28010_Gearbox_PB2179.pdf	6010 100 Gbps Gearbox Transceiver Application Note Rev - 6010 100 Gbps Gearbox Transceiver Application Note Rev 6010 Clocking Mode Application Note Rev - 6010 Clocking Mode Application Note Rev		Quick Setup Guide	Errata Errata Errata
2017/06/19	S28110	Inquire	19mm 324-pin HFCBGA	Datasheet	27.96	2.5, 1.2, 0.9	10	Yes	10x10	Yes	S28110+S28115_300dpi.png	Single-chip integrated bi-directional 100G transceiver for direct-detect applications CAUI and CPPI compliant 10-lane host & module interface operates from 9.95 Gbps to 11.22 Gbps OIF CEI-28G-SR compliant module interface supports 100GBASE-R4 at 25.78 Gbps OIF CEI-28G-SR compliant module interface supports OTU4 at 27.95 Gbps 3-Tap Transmit FIR (pre and post-cursor emphasis) on all 10G and 28G transmitters Programmable 28 Gbps output voltage to over 800mVpp Integrated CTLE and limiting amp on 10G and 28G receivers Receive eye monitors for in service link margin evaluation and receiver optimization Virtual lane identification and BIP error reporting in both 100GE and 2 x 40GE modes Any-to-any non blocking cross connect in 10 x 10G mode Reference clock at 1/16th, 1/32nd or 1/64th the host interface rate Flexible timing modes including reference timing and recovered clock timing	Product Brief	S2811x 100 Gb/s Gearbox 2 Power Distribution and Filtering PRELIMINARY v0.2 - S2811x 100 Gb/s Gearbox 2 Power Distribution and Filtering PRELIMINARY v0.2 S2811x 100 Gb/s Gearbox 2 Alarms and Fault Handling PRELIMINARY v0.1 - S2811x 100 Gb/s Gearbox 2 Alarms and Fault Handling PRELIMINARY v0.1		Quick Setup Guide	Errata Errata
2017/06/19	S28115	Inquire	19mm 324-pin HFCBGA	Datasheet	25.78	2.5, 1.2, 0.9	10	Yes	10x10	Yes	S28110+S28115_300dpi.png	XFI and SFP+ compliant 10-lane host interface OIF CEI-28G-SR compliant module interface OIF MLG 1.0 compliant in-band coding IEEE 802.3 Clause 49 compliant PCS on each 10GE input and output lane Provisionable lane alignment marker insertion in the MLG mux Provisionable lane physical lane assignment in the MLG demux 3-Tap Transmit FIR (pre and post-cursor emphasis) on all 10G and 28G transmitters Programmable 28 Gbps output voltage to over 800mVpp Integrated CTLE and limiting amp on 10G and 28G receivers Receive eye monitors for in service link margin evaluation and receiver optimization Virtual lane identification and BIP error reporting Reference clock at 1/16th, 1/32nd or 1/64th the host interface rate Flexible timing modes including reference timing and recovered clock timing Up to 6 optional clock outputs from any internal clock source	Product Brief	Application Note S2811x 100 Gb/s Gearbox 2 Alarms and Fault Handling PRELIMINARY v0.1 - S2811x 100 Gb/s Gearbox 2 Alarms and Fault Handling PRELIMINARY v0.1		Quick Setup Guide	Errata Errata
2017/06/22	S28032	Inquire	20mm 361-pin HFCBGA	Datasheet	31.79	2.5, 1.2, 0.95	1	Yes	1x1	Yes		100 Gbps PHY for metro & long haul applications generates four synchronous DQPSK pre-coded lanes for DP-QPSK modulation Operation from 111 Gbps to 127.16 Gbps to support FEC overhead CAUI and OTL-4.10 compliant 10-lane system interface, or 10-lane or 20-lane SFI-S system interface DP-DQPSK output drivers from 27.9 Gbps to 31.8 Gbps (per lane) with ± 2UI skew adjustment Transmit equalization to 3 dB Programmable output voltage to 800 mVppd Internal 100 Ω termination on CML inputs Three cross point switches to change multiplexing order Support for optional external VCXO for jitter compliance SPI interface to host controller Integrated per-lane PRBS generators and checkers -40°C to 85°C Industrial temperature range 20 x 20 mm, PBGA RoHS compliant package 3.2 W typical power in 10-lane mode	Product Brief
2017/06/22	QT2025	Buy	13mm 144-pin PBGA	Datasheet	10.52	1.8, 1.2	1	Yes	1x1	Yes	QT2025_300dpi.png	1G/10G: 1/10GE LAN/WAN & 1/10GFC Advanced EDC engine with auto tap weight adjustment & tracking 10G high-speed interface with integrated EDC and transmit wave shaping XAUI interface with equalization and transmit wave shaping Integrated loopbacks and test features Compliant to applicable IEEE & INCITS Specs	QT2025_PB3031 (1).pdf	QT2x25 QT2025/QT2035 Application Note Product Revision Differences: vA to vB January 16, 2008 QT2025/QT2035 Application Note Product Revision Differences: vA to vB January 16, 2008 Rev - QT2x25 QT2025/QT2035 Application Note Product Revision Differences: vA to vB January 16, 2008 QT2025/QT2035 Application Note Product Revision Differences: vA to vB January 16, 2008 Rev QT2025 Qt2025 SFP+ QRB Test Platform Training Material Using CX4 Connector Application Notes Rev 1 - QT2025 Qt2025 SFP+ QRB Test Platform Training Material Using CX4 Connector Application Notes Rev 1 QT2025 QT2025 Backplane Demo Instructions 2 Application Notes Rev 1 - QT2025 QT2025 Backplane Demo Instructions 2 Application Notes Rev 1 QT2x25 QT2025/35 B Version Synchronous Ethernet Support August 2007 QT2025/35 B Version Synchronous Ethernet Support August 2007 Rev - QT2x25 QT2025/35 B Version Synchronous Ethernet Support August 2007 QT2025/35 B Version Synchronous Ethernet Support August 2007 Rev QT2x25 QT2035S Evaluation Report - QT2035S – InfiniBand 1x Cable Testing v1.00 - 03.23.07 QT2035S Evaluation Report - QT2035S – InfiniBand 1x Cable Testing v1.00 - 03.23.07 Rev - QT2x25 QT2035S Evaluation Report - QT2035S – InfiniBand 1x Cable Testing v1.00 - 03.23.07 QT2035S Evaluation Report - QT2035S – InfiniBand 1x Cable Testing v1.00 - 03.23.07 Rev QT2x25 Potential Issue with QT2025, QT2225 & QT2035Firmware 2.0.3.0 and earlier - QT2x25 Potential Issue with QT2025, QT2225 & QT2035Firmware 2.0.3.0 and earlier QT2x25 QT2x25 - Application Note: AN3180 Trouble Shooting Guide - QT2x25 QT2x25 - Application Note: AN3180 Trouble Shooting Guide QT2x25 Controlling the INIT Driver Feature for Backplane Applications In f/w v33.0.0 - QT2x25 Controlling the INIT Driver Feature for Backplane Applications In f/w v33.0.0 QT2x25 QT2x25: Programming Application Note AN3174 v2.70 - QT2x25 QT2x25: Programming Application Note AN3174 v2.70 QT2x25 QT2x25 Application Note Frequently Asked Questions v1.00 - QT2x25 QT2x25 Application Note Frequently Asked Questions v1.00 QT2x25 QT2x25: 1GE Operation in Module Applications Application Note AN3178 v1.0 - QT2x25 QT2x25: 1GE Operation in Module Applications Application Note AN3178 v1.0 QT2x25 Understanding QT2x25 REFCLK Jitter Specifications v1.0 - QT2x25 Understanding QT2x25 REFCLK Jitter Specifications v1.0 QT2x25 QT2x25: Booting Options v2.1 - QT2x25 QT2x25: Booting Options v2.1 QT2x25 QT2025, QT2025-1, QT2225 Power Supply Filtering Rev 2.2 - QT2x25 QT2025, QT2025-1, QT2225 Power Supply Filtering Rev 2.2 QT2x25 QT2x25 Reset Issue on UC_I2C Bus January 23, 2009 - QT2x25 QT2x25 Reset Issue on UC_I2C Bus January 23, 2009 QT2x25 QT2xx5 Application Note Schematic and Layout Recommendations 12.08.08 - QT2x25 QT2xx5 Application Note Schematic and Layout Recommendations 12.08.08 QT2x25 Results for SFP+ 10GBASE-LRM, -SR, - LR SFP+ passive twinax cable Jun08 - QT2x25 Results for SFP+ 10GBASE-LRM, -SR, - LR SFP+ passive twinax cable Jun08 QT2x25 QT2025/-1, QT2225/-1 Evaluation Report/Interoperability Report v3.00 - QT2x25 QT2025/-1, QT2225/-1 Evaluation Report/Interoperability Report v3.00 QT2025 QT2025 Training Material - QT2025 QT2025 Training Material QT2025 QT2025 SFP+ Reference Design Schematic Images - QT2025 QT2025 SFP+ Reference Design Schematic Images	QT2025_UM3000_GUI.pdf QT2225_DEVICEvC_PRM3003.pdf QT2225_DEVICEvD_DB_PRM3103.pdf QT2025_DEVICEvB_PRM3000.pdf QT2025_DEVICEvC_PRM3004.pdf QT2025_DEVICEvD_DB_PRM3104.pdf QT2025_PRM3001_Revision_Differences_AtoB.pdf	Quick Setup Guide Quick Setup Guide Quick Setup Guide User's Guide Programmer's Reference Manual	QT2x25D_ERR3150.pdf QT2025_DEVICEvC_ERR3052_rev1_01.pdf QT2025_ERR3017_DEVICEvA.pdf	Evaluation Board User Guide	QT2025_OrcadSchematicLibrarySymbol.zip QT2025_DEVICEvA_BSDL2001.zip QT2225_1_SFP_Plus_Ref_SCH2022_ORCAD_121407.zip QT2225_BSDL2004_Device_vA.zip QT2225_OrcadLibrarySymbol.zip QT2x25_DEVICEvA_Firmware_v1_3_5.zip QT2x25_DEVICEvA_SPCE1802.zip QT2x25_DEVICEvB_C_LRMFirmware_v255_12_09.zip QT2x25_DEVICEvC_Firmware_v255_14_42.zip QT2x25_DEVICEvC_KRFirmware_v255_16_111.zip QT2x25_DEVICEvCandLater_SPCE1801.zip QT2x25_DEVICEvD_DB_Firmware_v2_0_3_2.zip QT2x25_DEVICEvD_DB_KRFirmware_v33_0_0.zip QT2x25_SynopsisVCSverilog_040709.zip QT2x25_VerilogModel_CadenceNC_VCS_Questa.zip
2017/06/22	QT2225	Buy	23mm 484-pin BGA	Datasheet	10.52	1.8, 1.2	2	Yes	2x2	Yes	QT2225_300dpi.png	Dual port 1G/10G: 1/10GE LAN/WAN & 1/10GFC Advanced EDC engine with auto tap weight adjustment & advanced tracking 10G high-speed interface with integrated EDC and transmit wave shaping XAUI interface with equalization and transmit wave shaping Integrated loopbacks and test features Compliant to applicable IEEE & INCITS Specs	QT2225_PB3033 (1).pdf	QT2x25_EDCRegisterAccessIssue_Summary.pdf QT2x25_AN3180_TroubleshootingGuide.pdf QT2x25 Controlling the INIT Driver Feature for Backplane Applications In f/w v33.0.0 - QT2x25 Controlling the INIT Driver Feature for Backplane Applications In f/w v33.0.0 QT2x25 QT2x25: Programming Application Note AN3174 v2.70 - QT2x25 QT2x25: Programming Application Note AN3174 v2.70 QT2x25 QT2x25 Application Note Frequently Asked Questions v1.00 - QT2x25 QT2x25 Application Note Frequently Asked Questions v1.00 QT2x25 QT2x25: 1GE Operation in Module Applications Application Note AN3178 v1.0 - QT2x25 QT2x25: 1GE Operation in Module Applications Application Note AN3178 v1.0 QT2x25 Understanding QT2x25 REFCLK Jitter Specifications v1.0 - QT2x25 Understanding QT2x25 REFCLK Jitter Specifications v1.0 QT2x25 QT2x25: Booting Options v2.1 - QT2x25 QT2x25: Booting Options v2.1 QT2x25 QT2025, QT2025-1, QT2225 Power Supply Filtering Rev 2.2 - QT2x25 QT2025, QT2025-1, QT2225 Power Supply Filtering Rev 2.2 QT2x25_UC_I2C_Reset_AN3169.pdf QT2x25 QT2xx5 Application Note Schematic and Layout Recommendations 12.08.08 - QT2x25 QT2xx5 Application Note Schematic and Layout Recommendations 12.08.08 QT2x25 Results for SFP+ 10GBASE-LRM, -SR, - LR SFP+ passive twinax cable Jun08 - QT2x25 Results for SFP+ 10GBASE-LRM, -SR, - LR SFP+ passive twinax cable Jun08 QT2x25 QT2025/-1, QT2225/-1 Evaluation Report/Interoperability Report v3.00 - QT2x25 QT2025/-1, QT2225/-1 Evaluation Report/Interoperability Report v3.00					QT2025_OrcadSchematicLibrarySymbol.zip QT2225_OrcadLibrarySymbol.zip QT2x25_DEVICEvA_Firmware_v1_3_5.zip QT2x25_DEVICEvB_C_LRMFirmware_v255_12_09.zip QT2x25_DEVICEvC_Firmware_v255_14_42.zip QT2x25_DEVICEvC_KRFirmware_v255_16_111.zip QT2x25_DEVICEvD_DB_Firmware_v2_0_3_2.zip QT2x25_DEVICEvD_DB_KRFirmware_v33_0_0.zip QT2x25_SynopsisVCSverilog_040709.zip QT2x25_VerilogModel_CadenceNC_VCS_Questa.zip
2017/08/29	MATP-10025	Inquire	BGA	MATP10025.pdf							PRISM_angled.png	1 x 53 Gbaud PAM-4 Network Interface 4 x 25 Gbps Host Interface DSP for 2 km reach over SMF Integrated FEC Integrated Linear Modulator Driver PAM-4 test and diagnostic features 10 x 10 mm BGA								6011252408001

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