42 Mbps to 3.2 Gbps Quad Multi-Rate CDR
The M21012 is a high-performance quad multi-rate clock and data recovery (CDR) array, optimized for multi-lane telecom, and datacom applications. Each channel has an independent multi-rate CDR capable of operating at data-rates between 42 Mbps and 3.2 Gbps, allowing maximum flexibility in system design. The M21011 is rated for operation in the range of 1 Gbps to 3.2 Gbps. The M21001 is rated for operation in the range of 42 Mbps to 800 Mbps. Aside from the difference in supported signal data-rates, the M21012, M21011, and M21001 are identical. Signal conditioning features include adaptive input equalization and output pre-emphasis, allowing robust reception and transmission of signals to other devices up to 60° away. User-selectable input interface types allow DC-coupled input to CML, LVDS, and LVPECL. The outputs can also be DC-coupled to CML, LVDS and LVPECL. Frequency acquisition can be accomplished with or without an external reference clock. The built-in frequency synthesizer allows multi-rate operation, while operating with a single reference clock. The device can be controlled either through hardwired pins or an I2C-compatible interface. The hardwired mode eliminates the need for an external micro-controller, while allowing control of the key features of the device. The I2C-compatible interface allows complete control of the device features.
- Part Number
- 42 Mbps to 3.2 Gbps Quad Multi-Rate CDR
- Max Data Rate(Gbps)
- Number of Channels
- Package Type
- Four independent Multi-Rate CDRs capable of running between 42 Mbps and 3.2 Gbps
- Built-in pattern generator and receiver for module and system testing
- Typical Total Power Consumption as low as 390 mW with all channels running
- Operation with or without a Reference Clock
- Signal conditioning features for superior performance on trace lengths of up to 60?
- Jitter generation 4.5 mUI, Jitter Tolerance 0.65 UI typical
- Flexible Control through I2C-compatible interface or hardwired pins
- Flexible DC-Coupled input interface to CML, LVPECL, and LVDS