The M21250 is a high-performance quad multi-rate clock and data recovery (CDR)array, optimized for multi-lane video, telecom and datacom applications. Each CDR operates independently at bit rates between 42 Mbps to 3.2 Gbps, allowing maximum flexibility in system design. Signal conditioning features include adaptive input equalization and output pre-emphasis, allowing robust reception and transmission of signals to other devices up to 60" away.
Very low power dissipation and flexible power supply support for reduced power supply and thermal management costs
BIST features for PCB and system testing with fully independent transmitter and receiver: PRBS : 27 -1, 215 -1, 223 -1, 231 -1, 8b/10 : CJTPAT, CRPAT, countdown
Integrated signal conditioning for improved signal integrity with inexpensive PCB materials for longer PCB trace lengths: Input equalization : Up to 60° with FR4 at 3.2 Gbps, Output pre-emphasis Up to 40° with FR4 at 3.2 Gbps
PCB layout friendly with 'pass through' I/O and high speed output polarity inversion
Serial SPI 4 wire interface or hardwired interface control
Flexible I/O interfacing to CML, LVDS, and LVPECL with per channel output amplitude control
Integrated loop filter components and I/O termination resistors for simplified PCB designs and reduced cost
Superior jitter generation (5mUI typical) and improved jitter tolerance in the high frequency band